1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display in which each of the pixels comprising the liquid crystal display has the same parasitic capacitance.
2. Description of Related Art
A TFT-LCD (thin film transistor liquid crystal display) is a display in which thin film transistors serve as switching elements for a plurality of pixels so as to control an electro-optic effect of liquid crystal material. The display includes a multiplicity of pixels, each having a thin film transistor, a pixel electrode and a storage capacitor; a color filter device wherein the common electrode and the color filter are formed; and liquid crystal material sealed in the color filter device. In this type of LCD, each pixel generally contains a number of capacitors, such as, for example, a liquid crystal capacitor formed by a TFT matrix circuit glass plate and a color filter glass plate with the liquid crystal layer in between; a maintenance capacitor formed by the pixel electrode and a maintenance electrode; and a parasitic capacitor formed by a gate electrode, a source electrode and a drain electrode.
The parasitic capacitance will be described in detail with reference to FIG. 1, which is a cross-sectional view of a conventional TFT.
As illustrated in FIG. 1, the thin film transistor comprises a gate electrode 2, a source electrode 6 and a drain electrode 7 formed on transparent glass substrate 1. A gate isolation layer 3 covers gate electrode 2, and, on gate isolation layer 3, a channel layer 4 is formed with amorphous silicon such that it is situated above the upper part of gate electrode 2.
Channel layer 4, being connected with source electrode 6 and drain electrode 7 through contact layer 5, is composed of n.sup.+ -amorphous silicon. Drain electrode 7 is further connected with a pixel electrode 8.
As shown in FIG. 1, which is a cross sectional view of a TFT in FIG. 2, a portion "b" of drain electrode 7 overlaps gate electrode 2 to form a capacitor. This is what is commonly called a parasitic capacitor, the capacitance of which is called parasitic capacitance.
This parasitic capacitance has the following effect. When voltage is applied to the gate electrode of the TFT, an alternating current signal, shifted between source electrode 6 and drain electrode 7, is transitionally transmitted to the liquid crystal capacitor, the parasitic capacitor, and to the storage capacitor. The parasitic capacitance of a TFT is normally greater than that of a MOSFET, such that the wave pattern of this alternating current signal becomes anti-symmetrical. Resulting from this anti-symmetrical signal phenomenon is an offset voltage problem and undesired flickering.
To attempt to overcome these problems, a compensating voltage is applied to an electrode situated at the opposite end of the liquid crystal layer. However, by undertaking this countermeasure, other problems arise. For example, when a plurality of pixels are formed on a TFT substrate, parasitic capacitors are formed in each of the pixels as a result of overlapping portions of drain electrode 7 with gate electrode 2, as shown in FIG. 1. Further, when the drain electrode and the gate electrode are misaligned, due to slight alignment errors during processing, such as misalignment during patterning layers using a photolithographic process, the parasitic capacitance values can be vary from pixel to pixel. This problem is exacerbated when the voltage applied to the opposite electrode is unable to compensate for the offset voltages caused by all of the different parasitic capacitance values and is only able to compensate for some of the different parasitic capacitance values.
Therefore, in addition to compensating for the offset voltages arising from the parasitic capacitance, it is necessary to form pixels having equal parasitic capacitance in order to solve the above-mentioned problem. The method as described in FIG. 2 is suggested in Korean Patent Public Information and Public Announcement Number 94-6989.
In the conventional method shown in FIG. 2, each pixel comprises, at least, one pair of TFTs. The two transistors are formed symmetrically with respect to middle line (A--A) which is parallel to data line 14. Gate electrode 12 for both TFTs is formed such that it perpendicularly extends from two different parts of a single gate line 11 and is symmetrical with respect to middle line (A--A). Drain electrode 13, connected with the pixel electrode (not drawn), is symmetrical with respect to, and formed along, middle line (A--A), parallel to data line 14. So, the left part of drain electrode section 13, with respect to the middle line (A--A), acts as a drain electrode for the left TFT, and the right part of drain electrode section 13 acts as a drain electrode for the right TFT.
Finally, as shown in FIG. 2, the conventional structure includes source electrodes 16 and 15 of the left and right TFTs, respectively. Source electrode 15 of the right TFT is formed perpendicularly to data line 14 and parallel with drain electrode 13, and source electrode 16 of the left TFT is formed perpendicularly to data line 14. The line connecting source electrode 15 of the right TFT with data line 14 crosses portions of gate electrode 12, then is angled toward the upper side and formed in parallel with drain electrode 13. Reference numeral 17, not described, indicates a channel layer formed by a semiconductor material.
A drawback of this conventional structure is that the area occupied by the TFTs increases. Further, when arranging pixels in a vertical stripe pattern, aperture efficiency decreases. Moreover, because the line connecting source electrode of the left transistor with the data line is formed to cross the two gate electrodes, the area of the gate electrode which is superposed by the source electrode increases, and as a result, a time constant of each wiring layer increases.